1. Field of the Invention
The invention relates to a filler circuit cell, and more particularly, to a filler circuit cell having a tie low circuit and a tie high circuit.
2. Description of the Prior Art
In current digital integrated circuit design, standard cell libraries are commonly used for achieving high automation in a layout design. As standard cell libraries often contain various kinds of commonly used cell types, such as basic logic gate circuits including AND, OR, NOT, layout engineers are able to take the advantage of these pre-existing cell types from the standard cell library and complete a layout design rapidly.
In order to suit the demand of the fabrication, every cell unit after being processed through a series of automotive tools is substantially rectangular, such that input/output (I/O) could be arranged on the periphery of the cell unit. In most cases, numerous gaps are found in each cell unit as a perfect rectangle is impossible to achieve. Filler circuit cells are utilized in this regard to fill the gaps within a cell unit thereby completing design request such as design rule check. Filler circuit cells are typically divided into two categories, including pattern type filler circuit cells and capacitor type filler circuit cell. Pattern type filler circuit cells do not include any real circuits therein, and are only utilized to fill the gaps within a cell unit. Capacitor type filler circuit cells on the other hand are utilized to provide stable voltage for the circuit such that the circuit between the I/O end and the cell unit is not affected by switching surge resulted from the voltage source.
Referring to FIG. 1, FIG. 1 illustrates a circuit diagram of utilizing MOS transistors to implement a capacitor type filler circuit cell according to the prior art. As shown in FIG. 1, the conventional filler circuit design includes a NMOS transistor 12, a PMOS transistor 14, and two voltage sources (Vdd/Vss) connected to the NMOS transistor 12 and the PMOS transistor 14 respectively. The NMOS transistor 12 includes a gate 16, a source 18, and a drain 18, in which the gate 16 is directly connected to the voltage source Vdd whereas the source 18 and the drain 18 is connected to the voltage source Vss. PMOS transistor 14 includes a gate 20, a source 22 and a drain 22, in which the gate 20 is directly connected to the voltage source Vss and the source 22 and the drain 22 is connected to the voltage source Vdd.
Despite the aforementioned filler circuit cell may be used to fill gaps within a cell unit, the conventional design of connecting the gate 16 of the NMOS transistor 12 and the gate 20 of the PMOS transistor 14 to the voltage source typically causes severe damage to the gate dielectric layer/inversion layer of the transistor as a sudden glitch is generated at either one of the voltage source. This results in breakdown of the entire transistor.